Job Description
Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something.
Description
Once you understand the details of design components and any associated system reference models, you will construct detailed test plans for various components of the design including use cases, through collaborative work with cross-functional teams. You will create coverage driven verification plans from specifications, review with multi-functional teams and refine to achieve coverage targets. You will architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and reference models. Working closely with DV methodology architects, you will improve verification flow. In this role, you will also execute test plans from RTL simulation bring-up to sign-off, report and debug failures, maintain regressions and report the verification progress against test plans and coverage metrics.
Minimum Qualifications
- Bachelor of Science degree and 3+ years of relevant industry experience.
- Strong knowledge of System Verilog and UVM.
- Good understanding of System C, C/C++, Python/perl.
- Experience in developing and establishing DV Methodologies.
- Ability to develop System Verilog Testbench with UVM methodology from scratch.
- Experience with constraint random testing, SVA, Coverage driven verification.
- Good test planning and problem-solving skills.
Key Qualifications
Preferred Qualifications
- Master of Science degree in Electrical Engineering/Computer Science.
- Experience in C/C++ modeling for design verification.
- Knowledge of 4G/5G cellular physical layer operation (3GPP).
- Experience with verification of embedded processor cores.
- Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
Education & Experience
Additional Requirements
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $135,400 and $250,600, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
- Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
Once you understand the details of design components and any associated system reference models, you will construct detailed test plans for various components of the design including use cases, through collaborative work with cross-functional teams. You will create coverage driven verification plans from specifications, review with multi-functional teams and refine to achieve coverage targets. You will architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and reference models. Working closely with DV methodology architects, you will improve verification flow. In this role, you will also execute test plans from RTL simulation bring-up to sign-off, report and debug failures, maintain regressions and report the verification progress against test plans and coverage metrics.
Job Tags
Relocation, Night shift,